Microchip Technology /ATSAME70J20 /TWIHS0 /IDR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (UNRE)UNRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCL_WS)SCL_WS 0 (EOSACC)EOSACC 0 (MCACK)MCACK 0 (TOUT)TOUT 0 (PECERR)PECERR 0 (SMBDAM)SMBDAM 0 (SMBHHM)SMBHHM

Description

Interrupt Disable Register

Fields

TXCOMP

Transmission Completed Interrupt Disable

RXRDY

Receive Holding Register Ready Interrupt Disable

TXRDY

Transmit Holding Register Ready Interrupt Disable

SVACC

Slave Access Interrupt Disable

GACC

General Call Access Interrupt Disable

OVRE

Overrun Error Interrupt Disable

UNRE

Underrun Error Interrupt Disable

NACK

Not Acknowledge Interrupt Disable

ARBLST

Arbitration Lost Interrupt Disable

SCL_WS

Clock Wait State Interrupt Disable

EOSACC

End Of Slave Access Interrupt Disable

MCACK

Master Code Acknowledge Interrupt Disable

TOUT

Timeout Error Interrupt Disable

PECERR

PEC Error Interrupt Disable

SMBDAM

SMBus Default Address Match Interrupt Disable

SMBHHM

SMBus Host Header Address Match Interrupt Disable

Links

()